Hi, this is my weekly report this week.
Progress this week
I am constructing some converter blocks this week, which make it easir to interact with Verilog modules of different data widths.
I built the Double.v and Sync_fifo.v to test the general-axi block. But I think it still need some more complicated Verilog modules to make sure it works well.
I am working on the error handling part this week as well.
Plan next week
I think I can use Chisel, a higher level HDL(Hardware Description Language), to build some more complicated module to test the block.
Issue(s)
See you next week.
