Hi, This is my weekly report this week.
Progress this week
I built the overall structure of the verilog simulation block this week. you can find the report which discussed details about the structure here.
Plan next week
Build the Verilog_data, Shell_cmd and Shared_lib class. Implement them with default rules.
Issue(s)
After two weeks, I will have my final exam. I may need to take some time to review for the exam, but I think I can still catch up.
See you next week.
