Hi, This is my weekly report this week.
Progress this week
I have finished the tutorials from chapter 2 to chapter 6 this week.
I changed the module name gr-howto to gr-mytutorial.
Plan next week
Finish the tutorials chapter 7 left in the next week.
Try to make the Verilator related header file available in GNU Radio blocks.
Issue(s)
Verilator will compile Verilog file into C++, we could run simulation with the class it offers. But we do not know the member names(ports of Verilog module) in that class unless we have some way to parse either Verilator-generated C++ file or Verilog source file (Verilator do offer a XML file output which contains the class name, but this file changes with version of Verilator according to the author.). Due to the lack of reflection mechanism in C++, I may have to write the class names right in to code of simulation.
I need to extract the ports name which is clk rst_n dout in flicker.v. I am not sure, would it be appropriate if I just use regular expression to read the C++ header file shown below.
The Verilog source file is like:
module flicker(clk, rst_n, dout);
parameter WIDTH = 5;
input clk, rst_n;
output reg [WIDTH-1:0] dout;
//...
The Verilator generated C++ header file:
VL_MODULE(Vflicker) {
public:
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(rst_n,0,0);
VL_OUT8(dout,4,0);
//...
}
The XML file generated by Verilator:
<netlist>
<module fl="d1" name="flicker">
<var fl="d3" name="clk" dtype_id="1"/>
<var fl="d3" name="rst_n" dtype_id="1"/>
<var fl="d4" name="dout" dtype_id="2"/>
...
</module>
...
</netlist>
See you next week.
